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News & Events
Recent CECS News
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Students inducted into BME Honor Society
Congratulations to the following students inducted into the WSU chapter of Alpha Eta Mu Beta (AEMB) Biomedical Engineering Honor Society.
Juniors
Alexander Bhatia
Leah Hill
Benjamin Schmitt
Seniors
Joseph Grodecki
Korinne Lusterio
Rachel Mattis
Jason Monnin
Charles Stanford
Jessica Win
Zachary Wise
Graduate Students
Sangeetha Alladi
Stephanie Auld
Rohit Bhat
Rikki Chokshi
Maurissa D'Angelo
Priya Ganapathy
Shawn Gargac
Hrishikesh Karvir
Kara Muckley
Aarti Raheja
Grant Roush
Jennifer Serres
Amy Sipp
Bino Varghese
Betty Yang
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Skipper receives research grant
Dr. Julie Skipper (BIE) was among the first recipients of a $5,000 research grant from WSU's Women in Science Giving Circle (WISGC) to support graduate students. The WISGC strives to encourage more women to pursue STEM degrees by providing scholarships and research grants.
For more information on the Women in Science Giving Circle, please visit www.wright.edu/cosm/wgc
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Jennifer Engimann receives scholarship
Jennifer Engimann (CSE) was among the first recipients of a $1,500 scholarship from WSU's Women in Science Giving Circle (WISGC). The WISGC strives to encourage more women to pursue STEM degrees by providing scholarships and research grants.
For more information on the Women in Science Giving Circle, please visit www.wright.edu/cosm/wgc
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LawnBot Team brings home 1st Place win
 The 2008 WSU LawnBot team won first place for the second year in a row at the Institute of Navigation's (ION) Annual Robotic Lawn Mower Competition held June 5-8 at Siebenthaler's Garden Center in Beavercreek. The 1st place prize comes with a $15,000 award for the team.
Team members
Nicholas Baine (EE)
Jeffrey Baugher (EE)
Brian Birkmire (CEG)
Kurt Darding (ME)
Joseph Mertz (EE)
Joe Natarian (EE)
Veronica Rathbun (ME)
Kimberly Reichelderfer (ME)
Jonathan Roach (EE)
Nicholas Schwieterman (EE)
Errol Talbot (CEG)
Paul Tarka (CS)
Adam Webb (EE)
Faculty Advisors
Dr. Kuldip Rattan (EE)
Dr. Scott Thomas (MME)
Dr. John Gallagher (CSE)
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Kazimierczuk Receives ASEE Teaching Award
 Dr. Marian Kazimierczuk (EE) was recently selected as the recipient of the 2008 Outstanding Teaching Award by the North Central Section of the American Society for Engineering Education.
CECS Recent & Upcoming Events
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Basic Patent Research Workshop-June 18
Learn basic information about patents at free evening WSU workshop
Working on an idea for a new product but don’t know what to do next? The Wright State University Libraries is again helping beginning inventors learn what steps are needed to receive a patent for their ideas. A free patent research workshop is Wednesday evening, June 18th, from 6 to 9:00 p.m. in Room 241 of the Paul Laurence Dunbar Library on campus.
Designed for the novice inventor, the workshop offers basic patent information and search techniques for using the United States Patent and Trademark Office (USPTO) Web site and other databases. Literature from the USPTO will also be distributed during the workshop.
Wright State’s library is a U.S. Patent and Trademark Depository Library and houses one of the most powerful patent searching tools, PubWEST. It is the same patent database used by the patent examiners at the USPTO in Alexandria, Virginia.
Seating for the workshop is limited.
Register online at www.libraries.wright.edu/find/gov/patent/workshops.html or contact Ran Raider, patent and trademark reference specialist for the Paul Laurence Dunbar Library, at ran.raider@wright.edu or by calling (937) 775-3521.
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Linux Meeting - June 19
Linux meeting Thur. Jun. 19
The Dayton Linux Users Group (DLUG, a Special Interest Group of Dayton Microcomputer Association) meeting will be in Room 145 of Wright State University's Russ Engineering Center at 7:00 PM on Thursday, June 19.
We will devote the first 45 minutes to an hour of topics aimed at helping get new Linux users (newbies) up to speed, and include a short Q & A period. After that is the main presentation of more advanced topics. If you want to have a particular command, program, or topic discussed, or have any suggestions for future meetings, or wish to make a presentation, please contact the Linux-SIG Planning Team.
The topic for this month's meeting will be a panel discussion of "How to Introduce and Encourage Linux Use to Resistant Organizations". They will discuss experiences they have encountered when trying to start implementation of Linux projects and suggest how to improve them. Also, Michael Gilbert will continue his monthly "in-security" series - security issues that have popped up within the past month.
We would like to have a brief GPG key signing party. You will need to be present to participate and bring at least one form of government issued photo ID, printed copies (one for each participant - probably a dozen will be more than enough) of your Key ID, Key Type, Hex Fingerprint and Key Size info, and a pen
or pencil. See www.cryptnet.net/fdp/crypto/gpg-party.html#ss3.2 for details.
Dissertation Defense: Kumar Yelamarthi
Process Variation-Aware Timing Optimization with Load Balance of Multiple Paths in Dynamic and Mixed-Static-Dynamic CMOS Logic
Presented by Kumar Yelamarthi
Monday, June 16, 2008
1:00 PM
Tait Conference Room (405 Russ)
Faculty Advisor
Dr. Henry Chen (EE)
Abstract
The semiconductor technology has been advancing rapidly over the past decade to result in the design of several innovative applications. This advancement of semiconductor technology with the shrinking device, currently at 45 nanometers has allowed for placement of billions of transistor on a single microprocessor chip. This shrinking device size has presented the design engineers with two major challenges: 1) timing optimization at multiple giga-hertz frequencies, and 2) reducing the daunting effects of semiconductor process variations. Failure to account for the process variations often results in loss of design productivity by one generation, and might even result in catastrophic design failure.
This dissertation presents two timing optimization algorithms while accounting for process variations. The process variation-aware Load Balance of Multiple Paths (LBMP) algorithm is designed for timing optimization of dynamic CMOS circuits. Implemented on several dynamic CMOS circuits, the LBMP algorithm has demonstrated an average reduction in delay, uncertainty, and sensitivity from process variations by 48%, 57% and 14% respectively. The process variation-aware Path Oriented IN Time optimization flow for mixed-static-dynamic CMOS circuits partitions a design based on critical paths, chooses effective circuit style, and performs switch level timing optimization using the LBMP algorithm. Verified through implementation on several standard benchmark circuits, the POINT optimization flow has demonstrated an average reduction in delay and uncertainty from process variations by 17% and 13% over state-of-the-art commercial optimization tools.
Awards and Honors
- 2008 Graduate Student Achievement Award, Wright State University.
- 2008 Global Citizen Award, Wright State University.
- Outstanding Technical Director, American Society for Engineering Education North Central Section, March 2008.
- 2nd Best Student Paper Award, 2008 ASEE North Central Section Conference.
- Commendation from the Ohio Science and Engineering Alliance for instructional support at the Ohio Student Research Forum 2007.
- 2007 Dean’s commendation for advising a capstone senior design project at Wright State University.
- Commendation from Lt. General, USAF, for instructional support to the Wright STEPP program, 2006.
- 2004-05 WSU-CECS Excellence in Teaching Award for Graduate Teaching Assistants.
- 2003-04 WSU-CECS Dean’s Award for Excellence in Academics, Leadership, and Service to College.
- Finalist for WSU-CECS Excellence in Teaching Award in 2003-04, 2005-06.
Related Publications
- K. Yelamarthi and C-I. H. Chen, “A Path Oriented In Time Optimization Flow for Mixed-Static-Dynamic CMOS Logic,” accepted to present at IEEE Midwest Circuits and Systems Conference, August 2008.
- K. Yelamarthi and C-I. H. Chen, “Process Variation Aware Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization,” Journal of Computers, Academy Publishers, vol.3, no.2, pp.21-28, 2008.
- K. Yelamarthi and C-I. H. Chen, “Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic,” IEEE International Symposium on Quality Electronic Design, March 2008.
- K. Yelamarthi and C-I. H. Chen, “Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization,” IEEE International Symposium on Quality Electronic Design, March 2007.
- K. Yelamarthi and C-I. H. Chen, “A Sub-nanosecond Low-Power High-Performance 64-bit Adder,” IEEE International Conference on Computers and Devices for Communication, December 2006.
- S. Kakulavarapu, K. Yelamarthi, and C-I. H. Chen, “Signed Multiplier Using Baugh-Wooley and On-The-Fly Conversion Algorithms,” IEEE International Conference on Computers and Devices for Communication, December 2006.
- K. Yelamarthi and C-I. H. Chen, “Performance Optimization of Re-Convergent Manchester Carry Chain Adders,” Fifth IEEE Dallas Circuits and Systems Workshop, October 2006.
- V. Chandrasekhar, C-I. H. Chen and K. Yelamarthi, “Low-Cost Low-Power Self-Test Design and Verification for On-Chip ADC in System-On-a-Chip Applications,” IEEE Instrumentation and Measurement Technology Conference, April 2006.
- Other Publications = 20+
Related Presentations
- Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic, IEEE International Symposium on Quality Electronic Design, March 18, 2008.
- A Transistor Sizing Algorithm for Dynamic CMOS Circuits to improve Design for Manufacturability, 3rd Annual Dayton Engineering Sciences Symposium, October 29, 2007.
- Signed Multiplier Using Baugh-Wooley and On-The-Fly Conversion Algorithms, International Conference on Computers and Devices for Communication, December 20, 2006.
- A Sub-nanosecond Low-Power High-Performance 64-bit Adder, International Conference on Computers and Devices for Communication, December 18, 2006.
- Other Presentations = 15+
Also around the Russ Center...
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Dr. Farajian (MME) helps develop new way to assess nanocage capacity for hydrogen storage
Dr. Amir Farajian, an assistant professor in the Department of Mechanical and Materials Engineering, co-authored "Fullerene Nanocage Capacity for Hydrogen Storage" which appeared on the March 2008 cover of the American Chemical Society's journal Nano Letters. Nano Letters is a journal dedicated to nanoscience and nanotechnology. Farajian, co-authored the article with Dr. Boris Yakobson and Olga Pupysheva while he was a postdoctoral researcher at Rice University.
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